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? semiconductor components industries, llc, 2012 june, 2012 ? rev. 12 1 publication order number: n25s818ha/d n25s818ha 256 kb low power serial srams 32 k x 8 bit organization introduction the on semiconductor serial sram family includes several integrated memory devices including this 256 kb serially accessed static random access memory, internally organized as 32 k words by 8 bits. the devices are designed and fabricated using on semiconductor?s advanced cmos technology to provide both high ? speed performance and low power. the devices operate with a single chip select (cs ) input and use a simple serial peripheral interface (spi) serial bus. a single data in and data out line is used along with a clock to access data within the devices. the n25s818ha devices include a hold pin that allows communication to the device to be paused. while paused, input transitions will be ignored. the devices can operate over a wide temperature range of ? 40 c to +85 c and can be available in several standard package offerings. features ? power supply range: 1.7 to 1.95 v ? very low standby current: typical isb as low as 200 na ? very low operating current: as low as 3 ma ? simple memory control: single chip select (cs ) serial input (si) and serial output (so) ? flexible operating modes: word read and write page mode (32 word page) burst mode (full array) ? organization: 32 k x 8 bit ? self timed write cycles ? built ? in write protection (cs high) ? hold pin for pausing communication ? high reliability: unlimited write cycles ? green soic and tssop ? these devices are pb ? free, halogen free/bfr free and are rohs compliant http://onsemi.com tssop ? 8 t suffix case 948al marking diagrams c124 xxxxyzz xxxx = date code y = assembly code zz = lot traceability device package ordering information n25s818has21i soic ? 8 (pb ? free) shipping ? 100 units / tube soic ? 8 s suffix case 751bd N25S818HAT21I tssop ? 8 (pb ? free) 100 units / tube n25s818has21it soic ? 8 (pb ? free) 3000 / tape & reel N25S818HAT21It tssop ? 8 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. c114 xxxxyzz
n25s818ha http://onsemi.com 2 so nc vss vcc sck si cs hold vcc sck si hold so nc vss cs 1 1 soic ? 8 tssop ? 8 figure 1. pin connections (top view) table 1. device options part number density power supply (v) speed (mhz) package typical standby current read/write operating current n25s818has2 256 kb 1.8 16 soic 200 na 3 ma @ 1 mhz n25s818hat2 tssop table 2. pin names pin name pin function cs chip select input sck serial clock input si serial data input so serial data output hold hold input nc no connect v cc power v ss ground sram array decode logic clock circuitry sck data in receiver data out buffer figure 2. functional block diagram hold cs si so
n25s818ha http://onsemi.com 3 table 3. absolute maximum ratings item symbol rating unit voltage on any pin relative to v ss v in,out ?0.3 to v cc + 0.3 v voltage on v cc supply relative to v ss v cc ?0.3 to 4.5 v power dissipation p d 500 mw storage temperature t stg ?40 to 125 c operating temperature t a ? 40 to +85 c soldering temperature and time t solder 260 c, 10 sec c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. table 4. operating characteristics (over specified temperature range) item symbol test conditions min typ (note 1) max unit supply voltage v cc 1.8 v device 1.7 1.95 v input high voltage v ih 0.7 x v cc v cc + 0.3 v input low voltage v il ? 0.3 0.8 v output high voltage v oh i oh = ? 0.4 ma v cc ? 0.5 v output low voltage v ol i ol = 1 ma 0.2 v input leakage current i li cs = v cc , v in = 0 to v cc 0.5 a output leakage current i lo cs = v cc , v out = 0 to v cc 0.5 a read/write operating current i cc1 f = 1 mhz, i out = 0 3 ma i cc2 f = 10 mhz, i out = 0 6 ma i cc3 f = fclk max, i out = 0 10 ma standby current i sb cs = v cc , v in = v ss or v cc 200 500 na 1. typical values are measured at vcc = vcc typ., t a = 25 c and are not 100% tested. table 5. capacitance (note 2) item symbol test condition min max unit input capacitance c in v in = 0 v, f = 1 mhz, t a = 25 c 7 pf i/o capacitance c i/o v in = 0 v, f = 1 mhz, t a = 25 c 7 pf 2. these parameters are verified in device characterization and are not 100% tested
n25s818ha http://onsemi.com 4 table 6. timing test conditions item input pulse level 0.1 v cc to 0.9 v cc input rise and fall time 5 ns input and output timing reference levels 0.5 v cc output load cl = 100 pf operating temperature ? 40 to +85 c table 7. timing item symbol min max units clock frequency f clk 16 mhz clock rise time t r 2 s clock fall time t f 2 s clock high time t hi 32 ns clock low time t lo 32 ns clock delay time t cld 32 ns cs setup time t css 32 ns cs hold time t csh 50 ns cs disable time t csd 32 ns sck to cs t scs 5 ns data setup time t su 10 ns data hold time t hd 10 ns output valid from clock low t v 32 ns output hold time t ho 0 ns output disable time t dis 20 ns hold setup time t hs 10 ns hold hold time t hh 10 ns hold low to output high ? z t hz 10 ns hold high to output valid t hv 50 ns
n25s818ha http://onsemi.com 5 cs msb in sck so si lsb in high ? z figure 3. serial input timing cs msb out sck si so lsb out don?t care figure 4. serial output timing cs n+2 sck si so n+1 n high ? z nn ? 1 nn ? 1 n+2 n+1 n don?t care figure 5. hold timing t scs t csd t csh t cld t f t r t css t hd t su t dis t csh t v t lo t hi hold t su t hh t hs t hv t hs t hh t hz
n25s818ha http://onsemi.com 6 table 8. control signal descriptions signal name i/o description cs chip select i a low level selects the device and a high level puts the device in standby mode. if cs is brought high during a program cycle, the cycle will complete and then the device will enter standby mode. when cs is high, so is in high ? z. cs must be driven low after power ? up prior to any sequence being started. sck serial clock i synchronizes all activities between the memory and controller. all incoming addresses, data and instructions are latched on the rising edge of sck. data out is updated on so after the falling edge of sck. si serial data in i receives instructions, addresses and data on the rising edge of sck. so serial data out o data is transferred out after the falling edge of sck. hold hold i a high level is required for normal operation. once the device is selected and a serial sequence is started, this input may be taken low to pause serial communication without resetting the serial se- quence. the pin must be brought low while sck is low for immediate use. if sck is not low, the hold function will not be invoked until the next sck high to low transition. the device must remain selected during this sequence. so is high ? z during the hold time and si and sck are inputs are ignored. to resume operations, hold must be pulled high while the sck pin is low. lowering the hold input at any time will take to so output to high ? z. functional operation basic operation the 256 kb serial sram is designed to interface directly with a standard serial peripheral interface (spi) common on many standard micro ? controllers. it may also interface with other non ? spi ports by programming discrete i/o lines to operate the device. the serial sram contains an 8 ? bit instruction register and is accessed via the si pin. the cs pin must be low and the hold pin must be high for the entire operation. data is sampled on the first rising edge of sck after cs goes low. if the clock line is shared, the user can assert the hold input and place the device into a hold mode. after releasing the hold pin, the operation will resume from the point where it was held. the following table contains the possible instructions and formats. all instructions, addresses and data are transferred msb first and lsb last. table 9. instruction set instruction instruction format description read 0000 0011 read data from memory starting at selected address write 0000 0010 write data to memory starting at selected address rdsr 0000 0101 read status register wrsr 0000 0001 write status register read operations the serial sram read is selected by enabling cs low. first, the 8 ? bit read instruction is transmitted to the device followed by the 16 ? bit address with the msb being a don?t care. after the read instruction and addresses are sent, the data stored at that address in memory is shifted out on the so pin after the output valid time from the clock edge. if operating in page mode, after the initial word of data is shifted out, the data stored at the next memory location on the page can be read sequentially by continuing to provide clock pulses. the internal address pointer is automatically incremented to the next higher address on the page after each word of data is read out. this can be continued for the entire page length of 32 words long. at the end of the page, the addresses pointer will be wrapped to the 0 word address within the page and the operation can be continuously looped over the 32 words of the same page. if operating in burst mode, after the initial word of data is shifted out, the data stored at the next memory location can be read sequentially by continuing to provide clock pulses. the internal address pointer is automatically incremented to the next higher address after each word of data is read out. this can be continued for the entire array and when the highest address is reached (7fffh), the address counter wraps to the address 0000h. this allows the burst read cycle to be continued indefinitely. all read operations are terminated by pulling cs high.
n25s818ha http://onsemi.com 7 cs instruction si 04 3 25 169 810 7 11 sck 15 14 13 12 21 0 7 6543 210 high ? z 16 ? bit address data out so 21 23 22 24 28 29 30 31 26 27 25 000 0 0 011 figure 6. word read sequence cs instruction si 04 3 25 169 810 7 11 sck 15 14 13 12 210 7 6543 210 high ? z 16 ? bit address data out from addr 1 so 21 23 22 24 28 29 30 31 26 27 25 000 0 0011 7 6543 210 data out from addr 2 7 6543 210 7 6543 210 ... 32 34 33 35 39 40 41 42 37 38 36 43 45 44 46 47 don?t care don?t care addr 1 data out from addr n figure 7. page and burst read sequence data out from addr 3
n25s818ha http://onsemi.com 8 figure 8. page read sequence page x word y page x page x word y+1 page x word 31 page x word 0 page x word 1 si so data words: sequential, at the end of the page the address wraps back to the beginning of the page 16 ? bit address page address (x) word address (y) word y+2 figure 9. burst read sequence page x word y page x word 31 page x word y+1 page x word 0 page x+1 word y page x+1 word y+1 si so 16 ? bit address page address (x) word address (y) data words: sequential, at the end of the page the address wraps to the beginning of the page and continues incrementing up to the starting word address. at that time, the address increments to the next page and the burst continues. . . . page x word 1 . . . page x word y ? 1 write operations the serial sram write is selected by enabling cs low. first, the 8 ? bit write instruction is transmitted to the device followed by the 16 ? bit address with the msb being a don?t care. after the write instruction and addresses are sent, the data to be stored in memory is shifted in on the si pin. if operating in page mode, after the initial word of data is shifted in, additional data words can be written as long as the address requested is sequential on the same page. simply write the data on si pin and continue to provide clock pulses. the internal address pointer is automatically incremented to the next higher address on the page after each word of data is written in. this can be continued for the entire page length of 32 words long. at the end of the page, the addresses pointer will be wrapped to the 0 word address within the page and the operation can be continuously looped over the 32 words of the same page. the new data will replace data already stored in the memory locations. if operating in burst mode, after the initial word of data is shifted in, additional data words can be written to the next sequential memory locations by continuing to provide clock pulses. the internal address pointer is automatically incremented to the next higher address after each word of data is read out. this can be continued for the entire array and when the highest address is reached (7fffh), the address counter wraps to the address 0000h. this allows the burst write cycle to be continued indefinitely. again, the new data will replace data already stored in the memory locations. all write operations are terminated by pulling cs high. cs instruction si 04 3 25 169 810 7 11 sck 15 14 13 12 2107 6543 210 high ? z 16 ? bit address data in so 21 23 22 24 28 29 30 31 26 27 25 000 0 0010 ... figure 10. word write sequence
n25s818ha http://onsemi.com 9 cs instruction si 04 3 25 169 810 7 11 sck 15 14 13 12 210 7 6543 210 high ? z 16 ? bit address data in to addr 1 so 21 23 22 24 28 29 30 31 26 27 25 000 0 0010 7 6543 210 data in to addr 2 7 6543 210 7 6543 210 ... 32 34 33 35 39 40 41 42 37 38 36 43 45 44 46 47 addr 1 data in to addr 3 data in to addr n high ? z figure 11. page and burst write sequence 16 ? bit address page address (x) word address (y) page x word y page x word y+2 page x word y+1 page x word 31 page x word 0 page x word 1 si so data words: sequential, at the end of the page the address wraps back to the beginning of the page high ? z figure 12. page write sequence page x word y page x word 31 page x word y+1 page x word 0 page x+1 word y page x+1 word y+1 si so 16 ? bit address page address (x) word address (y) data words: sequential, at the end of the page the address wraps to the beginning of the page and continues incrementing up to the starting word address. at that time, the address increments to the next page and the burst continues. . . . page x word 1 . . . page x word y ? 1 high ? z figure 13. burst write sequence
n25s818ha http://onsemi.com 10 write status register instruction (wrsr) this instruction provides the ability to write the status register and select among several operating modes. several of the register bits must be set to a low ?0? if any of the other bits are written. the timing sequence to write to the status register is shown below, followed by the or ganization of the status register. cs instruction si 04 3 25 169 810 711 sck 7 6543 210 high ? z status register data in so 00 0 00 1 0 12 13 14 15 0 figure 14. write status register sequence bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 hold function 0 = hold (default) 1 = no hold reserved must = 0 reserved must = 0 mode 0 0 = word mode (default) 1 0 = page mode 0 1 = burst mode 1 1 = reserved figure 15. status register read status register instruction (rdsr) this instruction provides the ability to read the status register. the register may be read at any time by performing the following timing sequence. cs instruction si 04 3 25 169 810 711 sck 7 6543 210 high ? z status register data out so 00 0 00 1 0 12 13 14 15 1 figure 16. read status register instruction (rdsr) power ? up state the serial sram enters a know state at power ? up time. the device is in low ? power standby state with cs = 1. a low level on cs is required to enter an active state.
n25s818ha http://onsemi.com 11 package dimensions tssop8, 4.4x3 case 948al ? 01 issue o e1 e a2 a1 e b d c a top view side view end view 1 l1 l notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-153. symbol min nom max a a1 a2 b c d e e1 e l1 0o 8o l 0.05 0.80 0.19 0.09 0.50 2.90 6.30 4.30 0.65 bsc 1.00 ref 1.20 0.15 1.05 0.30 0.20 0.75 3.10 6.50 4.50 0.90 0.60 3.00 6.40 4.40
n25s818ha http://onsemi.com 12 package dimensions soic 8, 150 mils case 751bd ? 01 issue o e1 e a a1 h l c e b d pin # 1 identification top view side view end view notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec ms-012. symbol min nom max a a1 b c d e e1 e h 0o 8o 0.10 0.33 0.19 0.25 4.80 5.80 3.80 1.27 bsc 1.75 0.25 0.51 0.25 0.50 5.00 6.20 4.00 l 0.40 1.27 1.35 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 n25s818ha/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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